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SLG46127 Arkusz danych(PDF) 45 Page - Dialog Semiconductor

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SLG46127
11.4 ACMP1 Register Settings
Table 36. ACMP1 Register Settings
Signal Function
Register Bit
Address
Register Definition
ACMP1 In Voltage
Select
reg <371:367>
00000: 50 mV
00001: 100 mV
00010: 150 mV
00011: 200 mV
00100: 250 mV
00101: 300 mV
00110: 350 mV
00111: 400 mV
01000: 450 mV
01001: 500 mV
01010: 550 mV
01011: 600 mV
01100: 650 mV
01101: 700 mV
01110: 750 mV
01111: 800 mV
10000: 850 mV
10001: 900 mV
10010: 950 mV
10011: 1 V
10100: 1.05 V
10101: 1.1 V
10110: 1.15 V
10111: 1.2 V
11000: VDD/3
11001: VDD/4
11010: EXT_VREF (PIN1)
ACMP1 Hysteresis
Enable
reg <373:372>
00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: Enabled (200 mV)
ACMP1 Positive
Input Divider
reg <375:374>
00: 1.00X
01: 0.50X
10: 0.33X
11: 0.25X
ACMP1 Low
Bandwidth (Max: 1
MHz) Enable
reg <377>
1: On
0: Off
ACMP1 positive
input source select
PIN14 and Pin2
reg <378>
0: Pin2
1: Pin14


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