SLG46127 datasheet(30/88 Pages) DIALOG

Numer części	SLG46127

Szczegółowy opis	GreenPAK Programmable Mixed-signal Matrix

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000-0046127-101

Page 29 of 87

SLG46127

10.0 Combination Function Macro Cells

The SLG46127 has six combination function macrocells that can serve more than one logic or timing function. In each case, they

can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be

implemented in these macrocells;

•

Two macrocells that can serve as either 2-bit LUTs or as D Flip-Flops.

•

Two macrocells that can serve as either 3-bit LUTs or as D Flip-Flops.

•

One macrocell that can serve as either 3-bit LUT or as Pipe Delay

•

One macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter / Delays

Inputs/Outputs for the six combination function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of NVM bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

When used as a D Flip-Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from

the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have the option to connect both the

Q and Q Bar outputs to the connection matrix. The macrocells DFF2, DFF3 have an additional input from the matrix that can

serve as a nSET or nRST function to the macrocell.

The operation of the D Flip-Flop and Latch will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change

Latch: if CLK = 0, then Q = D

10.1 2-Bit LUT or D Flip-Flop Macrocells

There are two macrocells that can serve as either 2-bit LUTs or as D Flip-Flops. When used to implement LUT functions, the 2-bit

LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection

matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and

clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.

Figure 10. 2-bit LUT0 or DFF0

DFF0

CLK

D

2-bit LUT0 OUT

IN0

IN1

To Connection Matrix

Input <5>

4-bits NVM

From Connection Matrix Output <5>

1-bit NVM

reg <227:224>

reg <240>

From Connection Matrix Output <4>

Q/nQ

reg <225> Output Select (Q or nQ)

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