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SLG46169 Arkusz danych(PDF) 14 Page - Dialog Semiconductor |
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SLG46169 Arkusz danych(HTML) 14 Page - Dialog Semiconductor |
14 / 102 page 000-0046169-105 Page 13 of 101 SLG46169 5.9 Typical Pulse Width Performance 5.10 OSC Specifications time2 Delay, 3 cell mode: both edge delay, delayed edge detect output 1600 680 480 ns time2 Delay, 4 cell mode: both edge delay, delayed edge detect output 1900 815 600 ns Table 5. Typical Pulse Width Performance Parameter VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit Filtered Pulse Width for Filter 0 and Filter 1 < 150 < 55 < 35 ns Table 6. 25 kHz RC OSC frequency limits Power Supply Range (VDD) V Temperature Range +25 °C -40 °C ... +85 °C Minimum Value, kHz Maximum Value, kHz Minimum Value, kHz Maximum Value, kHz 1.8 V ±5% 24.044 25.969 19.924 29.122 3.3 V ±10% 24.395 25.609 20.383 28.363 5 V ±10% 24.297 25.702 20.371 28.337 2.5 V ... 4.5 V 24.163 25.873 20.288 28.397 1.71 V… 5.5 V 23.506 28.006 19.381 29.378 Table 7. 25 kHz RC OSC frequency error (error calculated relative to nominal value) Power Supply Range (VDD) V Temperature Range +25 °C -40 °C ... +85 °C Error (% at Minimum) Error (% at Maximum) Error (% at Minimum) Error (% at Maximum) 1.8 V ±5% -3.82% 3.88% -20.30% 16.49% 3.3 V ±10% -2.42% 2.44% -18.47% 13.45% 5 V ±10% -2.81% 2.81% -18.52% 13.35% 2.5 V ... 4.5 V -3.35% 3.49% -18.85% 13.58% 1.71 V… 5.5 V -5.98% 12.02% -22.48% 17.51% Table 4. Expected Delays and Widths for Programmable Delay (typical) Symbol Parameter Note VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit |
Podobny numer części - SLG46169 |
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Podobny opis - SLG46169 |
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