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SLG46200 Arkusz danych(PDF) 67 Page - Dialog Semiconductor

Numer części SLG46200
Szczegółowy opis  GreenPAK Programmable Mixed Signal Array
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Producent  DIALOG [Dialog Semiconductor]
Strona internetowa  http://www.dialog-semiconductor.com/
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SLG46200 Arkusz danych(HTML) 67 Page - Dialog Semiconductor

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SLG46200
reg<461>
CNT2 load signal tied to Ground
0: Off
1: Enable
reg<462>
CNT0 input clock source select
0: Internal oscillator clock
1: From matrix
reg<465:463>
CNT1 input clock source select:
000: Internal oscillator clock
001: Internal oscillator clock divided by 12
010: Internal oscillator clock divided by 4
011: CNT2 overflow signal
1X0: From matrix
1X1: From matrix divided by 8 and synchronized by internal clock
reg<466>
CNT2 input clock source select
0: Internal oscillator clock
1: From CNT0 output
reg<467>
Data source select for FSM (CNT2)
0: From external (though S2P module)
1: From internal ADC output
reg<469:468>
Delay mode select for DLY0:
00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
reg<471:470>
Delay mode select for DLY1:
00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
reg<473:472>
Delay mode select for DLY2:
00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
reg<474>
CNT0 and DLY0 output selection
0: Delay output
1: Counter output
reg<475>
CNT1 and DLY1 output selection
0: Delay output
1: Counter output
reg<476>
CNT2 and DLY2 output selection
0: Delay output
1: Counter output
reg<477>
PIN 4 digital out source selection
0: From connection matrix(out13)
1: ADC output clock
reg<478>
DLY1 And DLY2 Input Source Enable Control Signal
0: Disable DLY1 and DLY2 input
1: DLY1 input from connection matrix out10 and DLY2 input from connection matrix out11
reg<479>
Reserved
Bit Address
Definition


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