SLG46400 datasheet(46/95 Pages) DIALOG

Numer części	SLG46400

Szczegółowy opis	GreenPAK 2TM Rev.B Programmable Mixed Signal Array

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SLG46400

13.0 Counters/Delay Generators (CNT/DLY)

There are four configurable counters/delay generators in the SLG46400. Three of these four logic cells can be either a 14-bit

counter (CNT) or a delay generator (DLY) and one can be a 8-bit counter or delay generator independently of how the other three

logic cells are defined.

13.1 Counter Functionality

CNT0, CNT1 and CNT2 each have a 14-bit input data source, while CNT3 has a 8-bit input data source.

CNT2 and CNT3’s inputs can be sourced from the NVM, the ADC, or the S2P, while CNT0 and CNT1’s inputs can be sourced

from the connection matrix. The clock can be sourced from either the internal RC Oscillator (with data divider for CNT1) or from

another connection matrix output.

The counters output their data to either the PWM or to the S2P. The supported counter functions include (FSM only): count UP,

count DOWN, KEEP, and LOAD DATA (taken from ADC, S2P or Counter Data). The four counters can also function as frequency

dividers, FSM (CNT2 and CNT3), or PWM ramp (CNT1), while captured data is outputted to S2P.

In counter mode, it is in DOWN mode. the count UP/DOWN, KEEP, and LOAD signals in CNT2 and CNT3 must be tied to ground

and the RC OSC should be forced ON if the clock is sourced from the internal RC OSC for the counter to work.

For proper counter functionality, the force signals (CNT0_force reg<588>, CNT1_force reg<610>, CNT2_force reg<633>,

CNT3_force reg<655>) should be configured as “1” (Force Power On) for any block configured as counter.

Example:

for CNT3 to use the CNT/DLY block in Counter mode the following settings should be applied:

•

CNT/DLY3 Output Source Select (output_src_sel) set to Counter Mode (reg <656> = “1”)

•

CNT3 Enable (CNT3_force) set to Force Power On (reg <655> = “1”)

•

Reset Source (rst_src_sel) should be set to Edge Detect mode (reg<654> = “1”)

•

Edge Select can be set to Both, Falling, or Rising (reg <669:668>)

•

Additionally, make sure that RC Osc is in operating mode. The RC Osc may need to be set to Force On as well.

Since CNT1 and CNT2 can be used for a PWM ramp function, the PWM power down signal will control the force power to those

macro cells.

13.2 CNT2 and CNT3 Reset Source Select

When reg <632> = “1“ (for CNT2) or reg <654> = “1“ (for CNT3), the reset signal for CNT2 or CNT3 is sourced from the falling

and/or rising edge active signal from the connection matrix and only applies when used for counter function. When used in the

counter function and reg <632> / reg <654> = “0“ then the reset signal is sourced from the POR.

However when the counter cells are used for a delay function, reg <632> / reg <654> must be set to 0.

Podobny numer części - SLG46400

Producent	Numer części	Arkusz danych	Szczegółowy opis
Renesas Technology Corp	SLG46400	1Mb / 96P	GreenPAK 2TM Rev. B Programmable Mixed Signal Array November 15, 2018

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Podobny opis - SLG46400

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