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SLG46400 Arkusz danych(PDF) 88 Page - Dialog Semiconductor |
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SLG46400 Arkusz danych(HTML) 88 Page - Dialog Semiconductor |
88 / 95 page 000-0046400-109 Page 82 of 89 SLG46400 reg<698:696> PIN5 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: Low voltage digital in mode without Schmitt trigger 011: Reserved 100: Push pull current x2 101: Open drain mode 110: Reserved 111: Push pull mode reg<700:699> PIN5 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<701> PIN5 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<703:702> PIN6 initial state control 00: Floating 01: Ground 10: Power 11: Input reg<706:704> PIN6 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: ;ow voltage digital in mode without Schmitt trigger 011: Reserved 100: Push pull current x2 101: Open drain mode 110: Reserved 111: Push pull mode reg<708:707> PIN6 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<709> PIN6 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<710> PIN6 open drain double 0: Normal current 1: Double current reg<712:711> PIN6 digital output source selection 0x: From Connection Matrix (out25) 10: From S2P (MISO) 11: From ADC Serial Output reg<713> ADC Input Gain Range 0: 0 ~ 1V 1: 0 ~ 0.78V reg<714> ADC Mux Channel Selection 0: MUX Disabled, ADC will sample PIN 8 for IN+ 1: MUX Enabled, ADC will sample either PIN 8 or 9 for IN+ reg<715> ADC power down mode select 0: ADC slow power on mode 1: ADC fast power on mode Bit Address Register Definition |
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Podobny opis - SLG46400 |
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