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SLG46532 Arkusz danych(PDF) 84 Page - Dialog Semiconductor |
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SLG46532 Arkusz danych(HTML) 84 Page - Dialog Semiconductor |
84 / 184 page SLG46532_DS_108 Page 83 of 183 SLG46532 9.7.4 CNT/DLY Timing Diagrams Figure 29. Delay Mode Timing Figure 30. Counter Mode Timing delay_in RC osc: force power on (always running) Delay output Asynchronous delay variable Asynchronous delay variable delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period Delay mode (edge select: both, counter data:3) delay_in RC osc: auto power on (powers up from delay in) Delay output offset offset delay = offset + period x (counter data + 1) See offset in table 3 delay = offset + period x (counter data + 1) See offset in table 3 RESET_IN CLK Counter OUT Count start in 0 clk after reset 4 clk period pulse Count mode (count data:3), Counter reset (rising edge detect) |
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