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SLG46533 Arkusz danych(PDF) 79 Page - Dialog Semiconductor

Numer części SLG46533
Szczegółowy opis  GreenPAK Programmable Mixed-signal Matrix
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SLG46533 Arkusz danych(HTML) 79 Page - Dialog Semiconductor

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SLG46533
9.5.3 3-Bit LUT or 8-Bit Counter / Delay Macrocells Used as 8-Bit Counter / Delay Register Settings
Table 80. CNT/DLY2 Register Settings
Signal Function
Register Bit
Address
Register Definition
LUT3_5 or
Counter2 Select
reg<1198>
0: LUT3_5
1: Counter2
Delay2 Mode Select
or asynchronous
counter reset
reg<1273:1272> 00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges / counter high level reset
Counter/delay2
Clock Source Select
reg<1276:1274> 000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25MHz OSC clock
110: External Clock
111: Counter1 Overflow
Counter/delay2
Output Selection for
Counter mode
reg<1277>
0: Default Output
1: Edge Detector Output
Counter/delay2
Mode Selection
reg<1279:1278> 00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay2
Control Data
reg<1543:1536> 1 – 255
Table 81. CNT/DLY3 Register Settings
Signal Function
Register Bit
Address
Register Definition
LUT3_6 or
Counter3 Select
reg<1197>
0: LUT3_6
1: Counter3
Delay3 Mode Select
or asynchronous
counter reset
reg<1281:1280> 00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges / counter high level reset
Counter/delay3
Clock Source Select
reg<1284:1282> 000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: 25 MHz OSC clock
110: External Clock
111: Counter2 Overflow
Counter/delay3
Output Selection for
Counter mode
reg<1285>
0: Default Output
1: Edge Detector Output
Counter/delay2
Mode Selection
reg<1287:1286> 00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay3
Control Data
reg<1551:1544> 1 – 255


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