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GS7000-CQT Arkusz danych(PDF) 11 Page - List of Unclassifed Manufacturers |
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GS7000-CQT Arkusz danych(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 14 page 522 - 06 - 02 11 The figure below describes the relationship between the input parallel clock and the input parallel data. The input parallel data must be stable for 4ns prior to the rising edge of the PCLKIN (setup time), and for 4 ns following the rising edge of the PCLKIN (hold time). Fig. 22 Transmitter Setup and Hold Time TYPICAL APPLICATION CIRCUITS Typical Receiver Application Circuit with External Equalizer tHOLD = 4ns tSETUP = 4ns DIN(n) PCLKIN 27 28 29 30 31 32 33 34 35 36 37 38 39 GS7000 NC VEE3 SDO SDO VCC3 CD SMPTE NC NC PCLKOUT VDD VSS NC NC VEE1 C1 C2 VCC1 SDI SDI VCC2 PCLKIN VEE2 EQ Rx/Tx NC VCC VCC 220 100n VCC VCC 220 10k MODE 100n 100n LOCK CD 100n VCC PARALLEL DATA OUTPUTS VCC 75 75 100n 10k 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 VCC 33 10p PCLK OUT VCC AGC GND VCC DIN DIN GND VCC AGC TRISTATE CD DOUT DOUT CD-ADJ OEM GS9024 VCC 10n 100p VCC VCC VCC VCC 10n 10n 75 75 75 37.5 10n 10n 1u 75 10n 10n 475 475 2k 100n 10u VCC1 GND SSI-CD All resistors in ohms, all capacitors in farads, unless otherwise shown. 13 12 11 10 9 8 7 6 5 4 3 2 1 |
Podobny numer części - GS7000-CQT |
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Podobny opis - GS7000-CQT |
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