CY7C1460KV25 datasheet(10/32 Pages) CYPRESS

Numer części	CY7C1460KV25

Szczegółowy opis	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)

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Producent	CYPRESS [Cypress Semiconductor]

Strona internetowa	http://www.cypress.com

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10 / 32 page

Document Number: 001-66679 Rev. *J

Page 10 of 32

CY7C1460KV25/CY7C1462KV25

CY7C1460KVE25/CY7C1462KVE25

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are all asserted active, and (3) the write signal WE is

asserted LOW. The address presented to the address inputs is

loaded into the address register. The write signals are latched

into the control logic block.

On the subsequent clock rise the data lines are automatically

three-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1460KV25/CY7C1460KVE25

and DQa,b/DQPa,b for CY7C1462KV25/CY7C1462KVE25). In

addition,

the

address

for

the

subsequent

access

(read/write/deselect) is latched into the address register

(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1460KV25/CY7C1460KVE25

and DQa,b/DQPa,b for CY7C1462KV25/CY7C1462KVE25) (or a

subset for byte write operations, see Write Cycle Description

table for details) inputs is latched into the device and the write is

complete.

The data written during the write operation is controlled by BW

(BWa,b,c,d for CY7C1460KV25/CY7C1460KVE25 and BWa,b for

CY7C1462KV25/CY7C1462KVE25)

signals.

The

CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/

CY7C1462KVE25 provides byte write capability that is described

in the Write Cycle Description table. Asserting the write enable

input (WE) with the selected byte write select (BW) input will

selectively write to only the desired bytes. Bytes not selected

during a byte write operation will remain unaltered. A

synchronous self-timed write mechanism has been provided to

simplify the write operations. Byte write capability has been

included in order to greatly simplify read/modify/write

sequences, which can be reduced to simple byte write

operations.

Because the CY7C1460KV25/CY7C1462KV25/

CY7C1460KVE25/CY7C1462KVE25 are common I/O devices,

data should not be driven into the device while the outputs are

active. The output enable (OE) can be deasserted HIGH before

presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for

CY7C1460KV25/CY7C1460KVE25

and

DQa,b/DQPa,b for

CY7C1462KV25/CY7C1462KVE25) inputs. Doing so will

three-state the output drivers. As a safety precaution, DQ and

DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1460KV25/

CY7C1460KVE25 and DQa,b/DQPa,b for CY7C1462KV25/

CY7C1462KVE25) are automatically three-stated during the

data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/

CY7C1462KVE25 have an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to four

WRITE operations without reasserting the address inputs.

ADV/LD must be driven LOW in order to load the initial address,

as described in the Single Write Accesses section above. When

ADV/LD is driven HIGH on the subsequent clock rise, the chip

enables (CE1, CE2, and CE3) and WE inputs are ignored and the

burst counter is incremented. The correct BW (BWa,b,c,d for

CY7C1460KV25/CY7C1460KVE25

and

BWa,b

for

CY7C1462KV25/CY7C1462KVE25) inputs must be driven in

each cycle of the burst write in order to write the correct bytes of

data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected prior to entering the “sleep” mode. CE1, CE2,

and CE3, must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

On-Chip ECC

CY7C1460KVE25/CY7C1462KVE25 SRAMs include an on-chip

ECC algorithm that detects and corrects all single-bit memory

errors, including Soft Error Upset (SEU) events induced by

cosmic rays, alpha particles etc. The resulting Soft Error Rate

(SER) of these devices is anticipated to be <0.01 FITs/Mb a

4-order-of-magnitude improvement over comparable SRAMs

with no On-Chip ECC, which typically have an SER of

200 FITs/Mb or more. To protect the internal data, ECC parity bits

(invisible to the user) are used.

The

ECC

algorithm

does

not

correct

multi-bit

errors.However,Cypress SRAMs are architected in such a way

that a single SER event has a very low probability of causing a

multi-bit error across any data word. The extreme rarity of

multi-bit errors results in a SER of <0.01 FITs/Mb.

Podobny numer części - CY7C1460KV25

Producent	Numer części	Arkusz danych	Szczegółowy opis
Cypress Semiconductor	CY7C1460KV33	1,010Kb / 31P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460KV33-167AXC	1,010Kb / 31P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460KV33-167AXI	1,010Kb / 31P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460KV33-167BZC	1,010Kb / 31P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460KV33-200AXC	1,010Kb / 31P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)

More results

Podobny opis - CY7C1460KV25

Producent	Numer części	Arkusz danych	Szczegółowy opis
Cypress Semiconductor	CY7C1460KV33	1,010Kb / 31P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1460SV25	429Kb / 31P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1370KV33	999Kb / 32P	18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
	CY7C1440KV33	3Mb / 33P	36-Mbit (1M 횞 36/2M 횞 18) Pipelined Sync SRAM (With ECC)
	CY7C1461KV33	2Mb / 23P	36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM with NoBL??Architecture
	CY7C1370KV25	2Mb / 30P	18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1370B	759Kb / 27P	512K 횞 36/1M 횞 18 Pipelined SRAM with NoBL Architecture
	CY7C1371KV33	682Kb / 24P	18-Mbit (512K 횞 36/1M 횞 18) Flow-Through SRAM with NoBL??Architecture (With ECC)
	CY7C1441KV33	1Mb / 32P	36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM (With ECC)
	CY7C1460BV25	721Kb / 30P	36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture

More results

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Podobny numer części - CY7C1460KV25

Podobny opis - CY7C1460KV25

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