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CY7C1563XV18 Arkusz danych(PDF) 19 Page - Cypress Semiconductor

Numer części CY7C1563XV18
Szczegółowy opis  72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
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Producent  CYPRESS [Cypress Semiconductor]
Strona internetowa  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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Document Number: 001-70205 Rev. *G
Page 19 of 29
CY7C1563XV18/CY7C1565XV18
Power Up Sequence in QDR II+ Xtreme SRAM
QDR II+ Xtreme SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
Apply VDD before VDDQ.
Apply VDDQ before VREF or at the same time as VREF.
Drive DOFF HIGH.
Provide stable DOFF (HIGH), power and clock (K, K) for 100 s
to lock the PLL.
PLL Constraints
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
The PLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 100
s of stable clock
to relock to the desired clock frequency.
Figure 4. Power Up Waveforms


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