Document Number: 001-44060 Rev. *O

Page 9 of 31

CY7C1663KV18/CY7C1665KV18

Truth Table

The truth table for CY7C1663KV18, and CY7C1665KV18 follows. [3, 4, 5, 6, 7, 8]

Operation

K

RPS WPS

DQ

DQ

DQ

DQ

Write Cycle:

Load address on the rising

edge of K; input write data

on two consecutive K and

K rising edges.

L–H

H [9] L [10] D(A) at K(t + 1)

 D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)

Read Cycle:

(2.5 cycle Latency)

Load address on the rising

edge of K; wait two and

half cycles; read data on

two consecutive K and K

rising edges.

L–H

L [10]

X

Q(A) at K(t + 2)

 Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4)

NOP: No Operation

L–H

H

H

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

Standby: Clock Stopped

Stopped

X

X

Previous State

Previous State

Previous State

Previous State

Notes

3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

4. Device powers up deselected with the outputs in a tristate condition.

5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.

6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.

8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

9. If this signal was low to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

10. This signal was high on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the

second read or write request.