MP1497S – SYNCHRONOUS, STEP-DOWN CONVERTER WITH INTERNAL MOSFETS

MP1497S Rev. 1.01

www.MonolithicPower.com

9

9/7/2015

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2015 MPS. All Rights Reserved.

OPERATION

The

MP1497S

is

a

high-frequency,

synchronous, rectified, step-down, switch-mode

converter with built-in power MOSFETs. It

offers a very compact solution to achieve 3A

continuous output current with excellent load

and line regulation over a wide input supply

range.

The MP1497S operates in a fixed-frequency,

peak-current–control mode to regulate the

output voltage. The internal clock initiates a

PWM cycle. The integrated high-side power

MOSFET turns on and remains on until its

current reaches the value set by the COMP

voltage. When the power switch is off, it

remains off until the next clock cycle starts. If

the current in the power MOSFET does not

reach the COMP set current value within 95%

of one PWM period, the power MOSFET will be

forced to turn off.

Internal Regulator

The 5V internal regulator powers most of the

output decreases and requires a 0.1µF ceramic

decoupling capacitor.

Error Amplifier

The error amplifier compares the FB pin voltage

against the internal 0.8V reference (REF) and

outputs a COMP voltage that controls the

power MOSFET current. The optimized internal

compensation network minimizes the external

component counts and simplifies the control

loop design.

Enable/SYNC Control

EN is a digital control pin that turns the

regulator on and off. Drive EN high to turn on

the regulator, drive it low to turn it off. An

internal 1MΩ resistor from EN to GND allows

EN to float to shut down the chip.

The EN pin is clamped internally using a 6.5V

series-Zener-diode as shown in Figure 2.

Connecting the EN pin through a pullup resistor

input current to less than 100µA.

Connecting the EN pin directly to a voltage

source without any pullup resistor requires

limiting the amplitude of the voltage source to

below 6.5V to prevent damaging the Zener

diode.

EN/SYNC

EN LOGIC

Zener

6.5V-typ

GND

Figure 2: Zener Diode Circuit

For external clock synchronization, connect a

clock with a frequency range of 300kHz and

2MHz 2ms after the output voltage is set: The

internal clock rising edge will synchronize with

the external clock rising edge. Select an

external clock signal with a pulse-width less

than 1.7μs.

Under-Voltage Lockout

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP1497S UVLO comparator monitors the

output voltage of the internal regulator, VCC.

The UVLO rising threshold is about 3.9V while

its falling threshold is 3.25V.

External Soft-Start

Adjust the soft-start time by connecting a

capacitor from the SS pin to ground. When the

soft-start period starts, an internal 11µA current

source charges the external capacitor. The soft-

start capacitor connects to the non-inverting

input of the error amplifier. The soft-start period

lasts until the voltage on the soft-start capacitor

exceeds the reference voltage of 0.8V. At this

point, the non-inverting amplifier uses the

reference voltage. The soft-start time can be

calculated as:

SS

SS

0.8V C (nF)

t(ms)

11 A







Over-Current-Protection and Hiccup

The MP1497S has a cycle-by-cycle over-

current limit that protects against the inductor

current peak value exceeding the set current