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LR24C02 Arkusz danych(PDF) 5 Page - Leshan Radio Company |
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LR24C02 Arkusz danych(HTML) 5 Page - Leshan Radio Company |
5 / 15 page Figure 3: Output Acknowledge Device Addressing The 2K EEPROM device require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 ). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device add ress, the EEPROM will output a "0 ". If a compare is not made, the chip will return to a standby state. V2.1 5/15 LESHAN RADIO COMPANY, LTD. |
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