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S29GL01GP Arkusz danych(PDF) 1 Page - Cypress Semiconductor |
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S29GL01GP Arkusz danych(HTML) 1 Page - Cypress Semiconductor |
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1 / 82 page  Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-00886 Rev. *B Revised May 22, 2017 S29GL01GP S29GL512P S29GL256P S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology General Description The Cypress S29GL01G/512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These devices offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher density, better performance and lower power consumption. Distinctive Characteristics Single 3V read/program/erase (2.7-3.6 V) Enhanced VersatileI/O™ control – All input levels (address, control, and DQ input levels) and outputs are determined by voltage on VIO input. VIO range is 1.65 to VCC 90 nm MirrorBit process technology 8-word/16-byte page read buffer 32-word/64-byte write buffer reduces overall programming time for multiple-word updates Secured Silicon Sector region – 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number – Can be programmed and locked at the factory or by the customer Uniform 64 Kword/128 Kbyte Sector Architecture – S29GL01GP: One thousand twenty-four sectors – S29GL512P: Five hundred twelve sectors – S29GL256P: Two hundred fifty-six sectors – S29GL128P: One hundred twenty-eight sectors 100,000 erase cycles per sector typical 20-year data retention typical Offered Packages – 56-pin TSOP – 64-ball Fortified BGA Suspend and Resume commands for Program and Erase operations Write operation status bits indicate program and erase operation completion Unlock Bypass Program command to reduce programming time Support for CFI (Common Flash Interface) Persistent and Password methods of Advanced Sector Protection WP#/ACC input – Accelerates programming time (when VHH is applied) for greater throughput during system production – Protects first or last sector regardless of sector protection settings Hardware reset input (RESET#) resets device Ready/Busy# output (RY/BY#) detects program or erase cycle completion Performance Characteristics Notes 1. Access times are dependent on VCC and VIO operating ranges. See Ordering Information page for further details. Regulated VCC: VCC = 3.0–3.6 V. Full VCC: VCC = VIO = 2.7–3.6 V. VersatileIO VIO: VIO = 1.65–VCC, VCC = 2.7–3.6 V. 2. Contact a sales representative for availability. Maximum Read Access Times (ns) Density Voltage Range (1) Random Access Time (tACC) Page Access Time (tPACC) CE# Access Time (tCE) OE# Access Time (tOE) 128 & 256 Mb Regulated VCC 90 25 90 25 Full VCC 100/110 100/110 VersatileIO VIO 110 110 512 Mb Regulated VCC 100 25 100 25 Full VCC 110 110 VersatileIO VIO 120 120 1 Gb Regulated VCC 110 25 110 25 Full VCC 120 120 VersatileIO VIO 130 130 |
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