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74LV165A Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74LV165A Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 18 page 2003 Jul 23 2 Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165A FEATURES • Wide supply voltage range from 2.0 to 5.5 V • Complies with JEDEC standard: JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V) JESD8-1A (4.5 to 5.5 V). • 5.5 V tolerant inputs/outputs • CMOS LOW power consumption • Direct interface with TTL levels (2.7 to 3.6 V) • Power-down mode • Asynchronous 8-bit parallel load • Synchronous serial input • Latch-up performance exceeds 250 mA • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. DESCRIPTION The 74LV165A is a high-performance, low-power, low-voltage, Is-gate CMOS device and superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging current back flow through the device when it is powered down. The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When input PL is HIGH, data enters the register serially at the input DS and shifts one place to the right (Q0 →Q1→Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. The clock input is a gate-OR structure which allows one input to be used as an active LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the input CE should only take place while CP HIGH for predictable operation. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is Vi = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay VCC = 3.3 V; CL =15pF CE, CP to Q7, Q7 7.5 ns PL to Q7, Q7 8.0 ns D7 to Q7, Q7 8.5 ns fmax maximum clock frequency VCC = 3.3 V; CL = 15 pF 115 MHz CI input capacitance 3.0 pF CPD power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 24 pF |
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