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AUIRS1170S Arkusz danych(PDF) 20 Page - Infineon Technologies AG |
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AUIRS1170S Arkusz danych(HTML) 20 Page - Infineon Technologies AG |
20 / 28 page AUIRS1170S 20 Rev. 2.3 2016-09-03 Figure 13: practical secondary waveforms in a LLC converter To improve the noise rejection then a LP filter on Vds is suggested; the general rule is that filter cut-off frequency has to be set according to the fundamental frequency of the ringings (Fring): because it is a first order filter, its - 3dB frequency shall be at least a decade below the ringing fundamental. On the other side, the filter introduces delays at both turn-on and turn-off. An example is shown in figure 14. A filter with a cut-off frequency of 1MHz (100pF - 1.5kOhm ) introduces a turn- on delay of several hundred nsec (around 650ns). Fortunately such delay can be easily compensated by introducing a diode in parallel to the filter resistance, which quickly discharges Cf during the high to low Vds transition. The effect of such diode is shown in figure 15, where the turn-on delay is now only 134nsec. Neglecting for a moment the compensation enabled by the diode, the delay cannot become a significant part of the switching half cycle. The delay introduced by the filter (0 to 90%) is 2.3 * Rf*Cf. Assuming as a starting point that the delay must stay at least below 20% of the half PWM period (Tsw/2), which is about half of the delay shown in Fig.14, we have that: 1 2.3∗��������∗�������� ≥ 10 ������������ = 10 ∗ ������������ [1] The delay compensation forced by the diode will then further reduce the real delay, since the discharging equivalent resistance "Rd" of the diode in forward conduction will be used. Then the final approximated formula to determine the RC filter pole value is the following: 2.3 ∗ 10 2 ∗ ���� ������������ ≤ 1 2 ∗ ���� ∗ ���������������� = �������� ≤ �������������������� 10 A final verification of the best working value has to be carried on in the real application and a good compromise has to be found case by case. |
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