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AD9022SZ Arkusz danych(PDF) 3 Page - Analog Devices |
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AD9022SZ Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 12 page –3– ORDERING GUIDE Temperature Package Package Model Range Description Option AD9022AQ/BQ –25 °C to +85°C 28-Lead Ceramic DIP Q-28 AD9022AZ/BZ –25 °C to +85°C 28-Pin Ceramic Z-28 Leaded Chip Carrier AD9022SQ –55 °C to +125°C 28-Lead Ceramic DIP Q-28 AD9022SZ –55 °C to +125°C 28-Pin Ceramic Z-28 Leaded Chip Carrier N – 2 N – 1 DATA OUTPUT N N – 3 N N + 1 ANALOG IN tOD = 15–27.5 TYPICAL N + 2 tOD ENCODE ta ta = 0.7 TYPICAL AD9022 Timing Diagram ABSOLUTE MAXIMUM RATINGS 1 +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +1.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS to 0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature Range AD9022AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25 °C to +85°C AD9022SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55 °C to +125°C Maximum Junction Temperature 2 . . . . . . . . . . . . . . . . +175 °C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300 °C Storage Temperature Range . . . . . . . . . . . . –65 °C to +150°C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances: “Q” Package (Ceramic DIP): θ JC = 10 °C/W; θ JA = 35 °C/W. “Z” Package (Gullwing Surface Mount): θ JC = 13 °C/W; θ JA = 45 °C/W. AD9022 Test AD9022AQ/AZ AD9022BQ/BZ AD9022SQ/SZ Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Min Typ Max Units Two-Tone Intermodulation Distortion Rejection 3 +25 °C V 74 74 74 dBc DIGITAL OUTPUTS 1 Logic Compatibility TTL TTL TTL Logic “1” Voltage Full VI 2.4 2.4 2.4 V Logic “0” Voltage Full VI 0.5 0.5 0.5 V Output Coding Offset Binary Offset Binary Offset Binary POWER SUPPLY +VS Supply Voltage Full VI 4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25 mA +VS Supply Current Full VI 100 120 100 120 100 120 mA –VS Supply Voltage Full VI –5.45 –5.2 –4.95 –5.45 –5.2 –4.95 –5.45 –5.2 –4.95 mA –VS Supply Current Full VI 180 220 180 220 180 220 mA Power Dissipation Full VI 1.4 1.9 1.4 1.9 1.4 1.9 W Power Supply Rejection Ratio (PSRR) 4 Full V 32 32 32 mV/V NOTES 1AD9022 load is a single LS latch. 2RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. Tested at 55% duty cycle. 3Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale. 4PSRR is sensitivity of offset error to power supply variations within the 5% limits shown. Specifications subject to change without notice. REV. B |
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