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TD351IN Arkusz danych(PDF) 7 Page - STMicroelectronics |
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TD351IN Arkusz danych(HTML) 7 Page - STMicroelectronics |
7 / 12 page Timing Diagrams TD351 7/12 5 Timing Diagrams Figure 3: General turn-on and 2-level turn-off sequence Figure 4: input and output waveform dynamic parameters Figure 5: Minimum ON-time IN OUT Vce VH level Vge VH level VL level CLAMP VL level Ta Ta Clamp threshold LVOFF COFF Open Twin Twout Miller plateau (edge mode) OUT VH level VL level LVOFF Twout tdon tdoff tonmin Vton Vtoff tonmin IN Twin Vton Vtoff (level mode) IN IN OUT VH level CD VL level 2.5V Ta <Ta LVOFF Ta Ta Ta<Tin<(Ta+2.Rdel.Cd) Tin<Ta Tin>(Ta+2.Rdel.Cd) |
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