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TL16C2550 Arkusz danych(PDF) 11 Page - Texas Instruments |
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TL16C2550 Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 34 page www.ti.com TIMING REQUIREMENTS TL16C2550 SLWS161 – JUNE 2005 5 V Nomial PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VOH High-level output voltage(2) IOH = -4 mA 4 V VOL Low-level output voltage(2) IOL = 4 mA 0.4 V II Input current VCC = 5.25 V, VSS = 0, VI = 0 to 5.25 10 µA V, All other terminals floating IOZ High-impedance-state output current VCC = 5.25 V, VSS = 0, VI = 0 to 5.25 ±20 µA V, Chip slected in write mode or chip deselcted ICC Supply current VCC = 5.25 V, TA = 25°C, RXA, 24 mA RXB, DSRA, DSRB, CDA, CDB, CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, XTAL1 at 4 MHz, No load on outputs, Ci(CLK) Clock input impedance VCC = 0, VSS = 0, f = 1 MHz, TA = 15 20 pF 25°C, All other terminals grounded CO(CLK) Clock output impedance 20 30 pF CI Input impedance 6 10 pF CO Output impedance 10 20 pF (1) All typical values are at VCC = 5 V and TA = 25°C. (2) These parameters apply for all outputs except XTAL2. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LIMITS ALT. SYM- FIG- TEST PARAMETER 2.5 V 3.3 V 5 V UNIT BOL URE CONDITIONS MIN MAX MIN MAX MIN MAX tcR Cycle time, read (tw7 + td8 + td9) RC 87 ns tcW Cycle time, write (tw6 + td5 + td6) WC 87 ns tw1 Pulse duration, clock high tXH 5 f = 16 MHz Max, 25 ns VCC = 2.5 V tw2 Pulse duration, clock low tXL tw1 Pulse duration, clock high tXH 5 f = 20 MHz Max, 20 ns VCC = 3.3 V tw2 Pulse duration, clock low tXL tw1 Pulse duration, clock high tXH 5 f = 24 MHz Max, 18 ns VCC = 5 V tw2 Pulse duration, clock low tXL tw6 Pulse duration,IOW tIOW 6 40 ns tw7 Pulse duration, IOR tIOR 7 40 ns tw8 Pulse duration, RESET tRESET 1 µs tSU3 Setup time, data valid before IOW ↑ tDS 6 15 ns tSU4 Setup time, CTS ↑ before midpoint of 17 10 ns stop bit th3 Hold time, CS valid afterIOW ↑ tWCS 6 10 ns th4 Hold time, address valid after IOW ↑ tWA th5 Hold time, data valid after IOW ↑ tDH 6 5 ns th6 Hold time, chip select valid after IOR ↑ tRCS 7 10 ns th7 Hold time, address valid afterIOR ↑ tRA 7 20 ns td4 Delay time, CS valid before IOW ↓ tCSW 6 7 ns td5 Delay time, address valid before tAW IOW ↓ td7 Delay time, CS valid to IOR ↓ tCSR 7 7 ns td8 Delay time, address valid to IOR ↓ tAR td10 Delay time, IOR ↓ to data valid tRVD 7 CL = 75 pF 45 ns td11 Delay time, IOR ↑ to floating data tHZ 7 CL = 75 pF 20 ns 11 |
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