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H27UCG8T2BTR-BC Arkusz danych(PDF) 50 Page - Hynix Semiconductor |
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H27UCG8T2BTR-BC Arkusz danych(HTML) 50 Page - Hynix Semiconductor |
50 / 56 page H27UCG8T2BTR-BC 64Gb(8192M x 8bit) MLC NAND Flash Rev 0.1 / Oct. 2012 50 Figure 47 : Multi plane Copy-back program Figure 48 : Block Erase 4.15. Block Erase The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A23 to A34 is valid while A15 to A22 is ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase verify. Once the erase process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 46 details the sequence. |
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