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RT6203B Arkusz danych(PDF) 8 Page - Richtek Technology Corporation |
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RT6203B Arkusz danych(HTML) 8 Page - Richtek Technology Corporation |
8 / 22 page RT6203B 8 DS6203B-01 July 2017 www.richtek.com © Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Serial Interface (SDA AND SCL pins) Note 5 Low Level Input Voltage Low-Level VIL -- -- 0.9 V High-Level VIH 2.5 -- -- Hysteresis of Schmitt Trigger Inputs VHYS 0.16 -- -- V Low Level SDA Output Voltage (Open drain, 3mA sink current) VOL1 -- -- 0.4 V Pulse Width of Spikes Suppressed by Input Filter tSP 50 -- -- ns SCL Clock Frequency fSCL -- -- 400 kHz Hold Time (repeated) Start Condition tHD;STA 0.6 -- -- μs Low Period of SCL Clock tLOW 1.3 -- -- μs High Period of SCL Clock tHIGH 0.6 -- -- μs Set-Up Time for a Repeated Start Condition tSU;STA 0.6 -- -- μs Data Hold Time tHD;DAT 50 -- 900 ns Data Set-Up Time tSU;DAT 100 -- -- ns Rise Time (SDA or SCL) tR 20 + 0.1Cb -- 300 ns Fall time (SDA or SCL) tF 20 + 0.1Cb -- 300 ns Set-Up Time for STOP Condition tSU;STO 0.6 -- -- μs Bus Free Time between STOP and START Condition tBUF 1.3 -- -- μs Capacitive Load for Each Bus Line Cb -- -- 400 pF SDA SCL tF tLOW tHD,STA tHD,DAT tHIGH tSU,DAT tSU,STA tHD,STA tSP tBUF tSU,STO PS tR Sr S tF tR |
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