High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
P 1
DESCRIPTION
The CS18LV10245 is a high performance, high speed and super low power CMOS Static
Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of
4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy
memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE).
The CS18LV10245 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin
sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.
FEATURES
1.
Fully static operation and Tri-state output
2.
TTL compatible inputs and outputs
3.
Ultra low power consumption :
2.0V (min) data retention
Low operation voltage : 4.5 ~ 5.5V ; 5mA@1MHz (Max.) operating current (Vcc = 5.0V)
4.
Standby Typ. = 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25
0C)
5.
Standard pin configuration
32 - SOP 450mil
32 - sTSOP-I - 8X13.4mm
32 - TSOP-I 8X20mm
32 - PDIP 600mil
Product Family
Part No.
Operating Temp Vcc. Range Speed (ns)
Standby (Typ.)
Package Type
CS18LV10245CC
32 SOP
CS18LV10245DC
32 STSOP
CS18LV10245EC
32 TSOP (I)
CS18LV10245LC
0~70
oC
0.50uA
32 PDIP
CS18LV10245CI
32 SOP
CS18LV10245DI
32 STSOP
CS18LV10245EI
32 TSOP (I)
CS18LV10245LI
-40~85
oC
4.5 ~ 5.5
55/70
0.80uA
32 PDIP
Note: Green package part no, sees order information.