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GD5F1GQ4REFIG Arkusz danych(PDF) 12 Page - GigaDevice Semiconductor (Beijing) Inc.

Numer części GD5F1GQ4REFIG
Szczegółowy opis  SPI(x1/x2/x4) NAND Flash
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Producent  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Strona internetowa  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD5F1GQ4REFIG Arkusz danych(HTML) 12 Page - GigaDevice Semiconductor (Beijing) Inc.

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SPI(x1/x2/x4) NAND Flash
1G
12
4.2 HOLD Mode
The HOLD# signal goes low to stop any serial communications with the device, but doesn
’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low
(if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of
HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don
’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure4-2. Hold Condition
HOLD
HOLD
CS#
SCLK
HOLD#
4.3 Write Protection
SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock
bits (BP0, BP1, BP2 and INV, CMP) from being overwritten. If the BRWD bit is set to 1 and WP# is LOW, the block protect
bits cannot be altered.
4.4 Power Off Timing
Please do not turn off the power before Write/Erase operation is complete. Avoid using the device when the battery is low.
Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or
damage to data.


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