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GD25B32C Datasheet(Arkusz danych) 13 Page - GigaDevice Semiconductor (Beijing) Inc.

Numer części GD25B32C
Szczegółowy opis  3.3V Uniform Sector Dual and Quad Serial Flash
Pobierz  56 Pages
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Producent  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Strona internetowa  http://www.gigadevice.com/
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B32C
13
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be
followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command
sequence has been shifted in. For the commands of Read, Fast Read, Read Status Register or Release from Deep
Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read
instruction can be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high
to return to deselected status.
For the commands of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That means CS# must be driven high when the number of clock pulses after
CS# being driven low is an exact multiple of eight. For Page Program, if CS# is driven high at any time the input byte is not
a full byte, nothing will happen and WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Write Enable
06H
Write Disable
04H
Volatile SR
Write Enable
50H
Read Status Register-1
05H
(S7-S0)
(continuous)
Read Status Register-2
35H
(S15-S8)
(continuous)
Read Status Register-3
15H
(S23-S16)
(continuous)
Write Status Register-1
01H
S7-S0
Write Status Register-2
31H
S15-S8
Write Status Register-3
11H
S23-S16
Read Data
03H
A23-A16
A15-A8
A7-A0
(D7-D0)
(Next byte)
(continuous)
Fast Read
0BH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
(continuous)
Dual Output
Fast Read
3BH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(1)
(continuous)
Dual I/O
Fast Read
BBH
A23-A8(2)
A7-A0
M7-M0(2)
(D7-D0)(1)
(Next
byte)
(Next byte)
(continuous)
Quad Output
Fast Read
6BH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(3)
(continuous)
Quad I/O
Fast Read
EBH
A23-A0
M7-M0(4)
dummy(5)
(D7-D0)(3)
(Next
byte)
(Next byte)
(continuous)
Quad I/O Word
Fast Read(7)
E7H
A23-A0
M7-M0(4)
dummy(6)
(D7-D0)(3)
(Next
byte)
(Next byte)
(continuous)
Page Program
02H
A23-A16
A15-A8
A7-A0
D7-D0
Next byte
continuous
Quad Page Program
32H
A23-A16
A15-A8
A7-A0
D7-D0(3)
Next byte
continuous
Fast Page Program
F2H
A23-A16
A15-A8
A7-A0
D7-D0
Next byte
continuous
Sector Erase
20H
A23-A16
A15-A8
A7-A0
Block Erase(32K)
52H
A23-A16
A15-A8
A7-A0
Block Erase(64K)
D8H
A23-A16
A15-A8
A7-A0
Chip Erase
C7/60
H
Enable Reset
66H




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