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GD25B256D Datasheet(Arkusz danych) 57 Page - GigaDevice Semiconductor (Beijing) Inc.

Numer części GD25B256D
Szczegółowy opis  3.3V Uniform Sector Dual and Quad Serial Flash
Pobierz  82 Pages
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Producent  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Strona internetowa  http://www.gigadevice.com/
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B256D
57
Figure 65 Erase Security Registers command Sequence Diagram (ADS=0)
Figure 66 Erase Security Registers command Sequence Diagram (ADS=1)
7.34.
Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains
four pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch
(WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered
by driving CS# Low, followed by the command code (42H), three address Bytes and at least one data Byte on SI. As soon
as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program
Security Registers command will be ignored.
Table 19 Security Registers
Address
A23-16
A15-12
A11
A10-0
Security Register #1
00H
0 0 0 1
0
Byte Address
Security Register #2
00H
0 0 1 0
0
Byte Address
Security Register #3
00H
0 0 1 1
0
Byte Address
Command
0
1
2
3
4
5
6
7
44H
CS#
SCLK
SI
8
9
29 30 31
MSB
2
1
0
24 Bits Address
23 22
Command
0
1
2
3
4
5
6
7
44H
CS#
SCLK
SI
8
9
37 38 39
MSB
2
1
0
32 Bits Address
31 30




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