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GD25B257D Datasheet(Arkusz danych) 69 Page - GigaDevice Semiconductor (Beijing) Inc.

Numer części GD25B257D
Szczegółowy opis  3.3V Uniform Sector Dual and Quad Serial Flash
Pobierz  92 Pages
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Producent  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Strona internetowa  http://www.gigadevice.com/
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 69 page
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B257D
69
8.38.
Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
status (WEL), Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” command
sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low  Sending
Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take approximately
tRST /tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going
or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is
recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.
Figure 78. Enable Reset and Reset command Sequence Diagram
Note: Enable Reset (66H) and Reset (99H) commands have no effect when the device is in Quad I/O DTR Continuous
Read Mode. The only way to quit the Quad I/O DTR Continuous Read Mode is to set
the “Continuous Read Mode” bits (M5-
4) not equal to (1,0).
Command
0
1
2
3
4
5
6
7
66H
CS#
SCLK
SI
SO
High-Z
Command
0
1
2
3
4
5
6
7
99H




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