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GD25B257D Datasheet(Arkusz danych) 11 Page - GigaDevice Semiconductor (Beijing) Inc.

Numer części GD25B257D
Szczegółowy opis  3.3V Uniform Sector Dual and Quad Serial Flash
Pobierz  92 Pages
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Producent  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Strona internetowa  http://www.gigadevice.com/
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 11 page
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B257D
11
6. ECC Operation
Error Correction Codes (ECC) is a commonly used technique in non-volatile memory to reduce the device Bit Error
Rate (BER) during the device operation life and improve device reliability. To achieve error detection and correction,
redundancy data must be added to store the ECC calculation results for a given length of data. In GD25B257D, every
aligned 8-Byte data (A[2:0] = 0, 0, 0) stored in the memory array will be checked by the internal ECC engine using SEC-
DED (Single Error Correction
– Double Error Detection) Hsiao Codes algorithm. With 8-Byte ECC data granularity, ECC
calculation latency time can be minimized and highest level of data integrity can be preserved.
The default value of all memory data is FFH
(Erased) when the device is shipped from the factory. A “Page Program
(02H)” or a “Quad Page Program (32H)” command can be used to program the user data into the memory array. When
ECC is enabled (ECC=1 in Status Register), ECC calculation will be performed during the internal programming operation
and the results are stored in the redundancy or spare area of the memory array. It is necessary to program every page in
aligned 8-Byte granularity so that ECC engine can store the correct ECC information. It is also required that every aligned
8-Byte data granularity can only be programmed once to avoid additional ECC calculation in the same granularity resulting
incorrect ECC results. A technique previously known as “Incremental Byte/Bit Programming to the same Byte location”
cannot be used for GD25B257D when ECC is enabled.
During data read operations, the internal ECC engine will check the ECC results stored in the spare area and apply
necessary error correction or error detection to the main array data being read out. It is necessary to check the ECC Status
Bits (SEC and DED) in the Extended Register after every Read operation to see if the data read out contains any error or
not. A Read operation can start from any Byte address and continue through the entire memory array, so it is not necessary
to align the 8-Byte granularity boundary address to start a Read command.
Additional hardware monitoring of the ECC status can also be used to observe the ECC status in real time during any
data output. When configured, the ECS# (ECC Correction Signal) pin will be pulled low during any aligned 8-Byte data
output if it contains SEC or DED events.




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