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GD25LB32D Datasheet(Arkusz danych) 21 Page - GigaDevice Semiconductor (Beijing) Inc.

Numer części GD25LB32D
Szczegółowy opis  1.8V Uniform Sector Dual and Quad Serial Flash
Pobierz  67 Pages
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Producent  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Strona internetowa  http://www.gigadevice.com/
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 21 page
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1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LB32D
21
7.5. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must
be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR)
command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP bit will be cleared to 0 in either
SPI or QPI mode. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0
when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write
Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits.
Figure6. Write Status Register Sequence Diagram
Command
0
1
2
3
4
5
6
7
01H
CS#
SCLK
SI
SO
High-Z
8
9 10 11 12 13 14 15
MSB
7
6
5
4
3
2
1
0
Status Register in
16 17 18 19 20 21 22 23
15 14 13 12 11 10 9
8
Figure6a. Write Status Register Sequence Diagram (QPI)
CS#
SCLK
IO0
IO1
IO2
IO3
0
1
2
3
4
5
Command
01H
4
12
0
8
5
13
1
9
14
10
7
3
15
11
Status Register in
6
2




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