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MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
Revision 1.0
- 8 -
2000/11/15
to define whether these pins are input or output. Port6 is purely output.
Reg name
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PORT4
F30h(r/w)
P40
PORT4
F31h(r/w)
P41
PORT4
F32h(r/w)
P42
PORT4
F33h(r/w)
P43
PORT4
F34h(r/w)
P44
PORT4
F35h(r/w)
P45
PORT4
F36h(r/w)
P46
PORT4
F37h(r/w)
P47
PORT5
F38h(r/w)
P50
PORT5
F39h(r/w)
P51
PORT5
F3Ah(r/w)
P52
PORT5
F3Bh(r/w)
P53
PORT5
F3Ch(r/w)
P54
PORT5
F3Dh(r/w)
P55
PORT5
F3Eh(r/w)
P56
PORT5
F3Fh(r/w)
P57
PORT6
F28h(w)
P60
PORT6
F29h(w)
P61
PORT6
F2Ah(w)
P62
PORT4 (r/w) :
Port 4 data input/output value.
PORT5 (r/w) :
Port 5 data input/output value.
PORT6 (w) :
Port 6 data output value.
5. PWM DAC
Each PWM DAC output pulse width of the converter is controlled by an 8-bit register in XFR. The frequency
of PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is
253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if content of the DAC register is FFH. Writing
00H to DAC register generates stable low output.
Reg name
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DA0
F20h (r/w)
Pulse width of PWM DAC 0
DA1
F21h (r/w)
Pulse width of PWM DAC 1
DA2
F22h (r/w)
Pulse width of PWM DAC 2
DA3
F23h (r/w)
Pulse width of PWM DAC 3
DA0-3 (r/w) : The output pulse width control for DA0-3.
* All of PWM DAC converters are centered with value 80h after power on.