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MC100EP809FA Arkusz danych(PDF) 1 Page - ON Semiconductor |
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1 / 8 page © Semiconductor Components Industries, LLC, 2002 August, 2002 – Rev. 5 1 Publication Order Number: MC100EP809/D MC100EP809 3.3V1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable The MC100EP809 is a low skew 1–to–9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or PECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 8). The MC100EP809 guarantees low output–to–output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 W to ground instead of a standard HSTL configuration (See Figure 6). To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. Designers can take advantage of the EP809’s performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single–end by biasing the non–driven pin in an input pair (see Figure 7). • 100 ps Typical Device–to–Device Skew • 15 ps Typical Within Device Skew • HSTL Compatible Outputs Drive 50 W to Ground with no Offset Voltage • Maximum Frequency > 750 MHz • 850 ps Typical Propagation Delay • Fully Compatible with Micrel SY89809L • PECL and HSTL Mode Operating Range: V CCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V • Open Input Default State 32 1 MC100 AWLYYWW EP809 32–LEAD LQFP FA SUFFIX CASE 873A Device Package Shipping ORDERING INFORMATION MC100EP809FA LQFP–32 250 Units/Tray MC100EP809FAR2 LQFP–32 2000/Tape & Reel MARKING DIAGRAM* A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week *For additional information, see Application Note AND8002/D http://onsemi.com |
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