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TWR-LS1021A Arkusz danych(PDF) 69 Page - Freescale Semiconductor, Inc

Numer części TWR-LS1021A
Szczegółowy opis  TWR-LS1021A Reference Manual
Download  71 Pages
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Producent  FREESCALE [Freescale Semiconductor, Inc]
Strona internetowa  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

TWR-LS1021A Arkusz danych(HTML) 69 Page - Freescale Semiconductor, Inc

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Board Configuration and Debug Support
TWR-LS1021A Reference Manual, Rev. 0
5-4
Freescale Semiconductor
SW2[3]
OFF
RCW Source is SDHC
SDHC RCW_SEL
0 : SDHC disabled (default)
1 : SDHC enabled
SW2[4]
OFF
RCW Source is QSPI
QSPI RCW_SEL
0 : QSPI disabled (default)
1 : QSPI enabled
SW2[5]
ON
Bus select is NOR or QSPI
IFC/QSPI Bus selection
0 : IFC disabled, QSPI enabled
1 : IFC enabled, QSPI disabled (default)
SW2[6]
ON
LVDD&L1VDD selection is
2.5V or 3.3V
LVDD&L1VDD Voltage Selection
0 : 3.3V
1 : 2.5V (default)
SW2[7]
ON
IFC_CS1 or SPI1_PCS0
selection
IFC_CS1/SPI1_PCS0 Selection
0 : IFC_CS1 disabled, SPI1_PCS0 enabled
1 : IFC_CS1 enabled, SPI1_PCS0
disabled (default)
SW2[8]
ON
DIPSW_IN1
SDA_SWD_EN Control
0 : use K20 IO pin to control
SDA_SWD_EN
1 : tied to high to disable MBED connection
(default)
SW3[1]
OFF
96MHz SYSCLK select or not
96MHz SYSCLK Selection
0 : Do not select 96MHz as SYSCLK
(default)
1 : Select 96MHz as SYSCLK
SW3[2]
ON
TEST_SEL_DRV
Drive TEST_SEL signal
0 : Non-compliant mode to support
boundary scan.
1 : JTAG compliant mode (default)
SW3[3]
ON
CLKGEN_FS0
System clock frequency setting
CLKGEN_FS[0:1]
00 = 66.66MHz
01 = 80.00MHz
10 = 100.00MHz (default)
11 = 83.33MHz
SW3[4]
OFF
CLKGEN_FS1
System clock frequency setting
SW3[5]
OFF
NOR Bank Select
BANK_SEL
BANK_SEL
0 : Vbank0 (default)
1 : Vbank1
SW3[6]
OFF
Signal multiplexed selection
MUX_SEL
MUX_SEL
0 : PCIE1,SGMII1,PCIE2,SGMII2, RGMII, CAN3&4,
SAI1&2, LCD, LPUART1 (default)
1 : PCIE1,SATA,PCIE2,SGMII2, RGMII, CAN3&4,
CAN1&2, UCC1&3, SPI2
SW3[7]
OFF
Reserved
Must be 0 [OFF]
SW3[8]
ON
Reserved
Must be 1 [ON]
Switch
Settings
[OFF=0 ON=1]
Option
Description


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