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TSW140X Arkusz danych(PDF) 6 Page - Texas Instruments |
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TSW140X Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 35 page Hardware Configuration www.ti.com 2.2.3 Fuses Fuse F1 is in line with the EVM input power. This is used along with diode D14 to protect the board from surges and over voltage on the input power supply. Fuse F2, when installed, will provide 6 VDC to the DAC EVM interface connector J4. CAUTION When using this 6 VDC for a DAC EVM, make sure the DAC EVM power connection is removed. 2.3 LEDs Eleven LEDs are on the TSW1400EVM to indicate the presence of power and the state of the FPGA. The LED on the left edge of the board illuminates to indicate the presence of a 5-V power to the board after SW7 is placed in the “ON” position. LED D1 illuminates to indicate that the FPGA programming has completed and is now operational. USER_LED0 and LED1 indicate transmission of data samples over SPI interface. USER_LED2 turns off when the FPGA is in reset mode. USER_LED3 indicates the FPGA PLL1 is locked to the ADC input clock from port 0. USER_LED4 indicates the FPGA PLL2 is locked to the ADC input clock from port 1 or locked to the FPGACLK from the DAC when in the DAC mode. USER_LED5 indicates that the DDR memory initialization is complete and the interface is ready to use. USER_LED6 and LED7 indicate that the two SPI FIFO’s are empty. LED D10 indicates the presence of 6-V power to the DAC EVM interface connector J4. 2.4 Connectors The TSW1400 EVM has several connectors to allow for direct plug in of various TI CMOS and LVDS ADC and DAC EVMs. 2.4.1 Input LVDS ADC Interface Connector The connection between the TSW1400EVM and the ADC EVM to be tested is through a 128-pin High speed Samtec connector. 35 LVDS data pairs plus two LVDS clock pairs have a defined position in the connector pinout that is common between the TSW1400EVM and many TI ADC EVMs. For the parallel LVDS DDR data format, the bit clock runs at the same rate as the sample clock to the ADC. For the serial LVDS data format, the bit clock runs at a higher multiple of the ADC sample clock and is used to strobe the serial data into the TSW1400EVM and then de-serialize the data. For the serial LVDS data format, a second clock is provided, called the frame clock or FCLK, that runs at the sample rate and is used to delineate the sample boundaries in the serial data stream. The frame clock line can be used as a second clock in the parallel LVDS DDR format that uses two data buses. The data direction for the LVDS data pairs is always defined as the ADC EVM driving the signal through the connector to the TSW1400EVM FPGA, with integrated 100- Ω termination in the FPGA. For one-channel parallel DDR bit-wise data formats, eight of the LVDS data pairs are used to support up to 16-bit-resolution ADCs at up to 250-MHz sampling rates. For one-channel parallel DDR sample-wise data formats, 14 of the LVDS data pairs are used to support up to 14-bit-resolution ADCs at up to 500- MHz sampling rates. For two-channel parallel DDR bit-wise data formats, 14 of the LVDS data pairs are used to support two channels of 14-bit resolution at up to 250-MHz sampling rate. For serial data formats, eight of the LVDS data pairs support up to eight channels of one-wire serial ADCs at up to 65-MHz sampling rate or four channels of two-wire serial ADCs at up to 125-MHz sampling rates. Eight extra CMOS single-ended signals are defined in the Samtec connector that are sourced from the USB interface through the connector to the ADC EVM. These signals, in the future, will allow the GUI to control the SPI serial programming of the ADC for those ADC EVMs that support this feature. 6 TSW140x High Speed Data Capture/Pattern Generator Card SLWU079C – March 2012 – Revised January 2014 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated |
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