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DLPC900 Arkusz danych(PDF) 64 Page - Texas Instruments

Numer części DLPC900
Szczegółowy opis  DLPC900 Digital Controller for Advanced Light Control
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DLPC900 Arkusz danych(HTML) 64 Page - Texas Instruments

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0.1 PF
0.1 PF
100 PF
0.1 PF
R=0.36
F
F
F
F
0.1 PF
0.1 PF
Vcore
1.15 PLL1
1.15 PLL2
1.15 PLL3
VPLL
DLPC900
Regulator
Vout
GND
GND
GND
GND
GND
GND
1.15V
DC
GND
64
DLPC900
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
www.ti.com
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
10 Layout
10.1 Layout Guidelines
10.1.1 General PCB Recommendations
Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity.
10.1.2 PCB Layout Guidelines for Internal Controller PLL Power
The following are guidelines to achieve desired controller performance relative to internal PLLs:
The DLPC900 contains four PLLs (PLLM1, PLLM2, PLLD, and PLLS), each of which have a dedicated 1.15 V
digital supply; three of these PLLs (PLLM1, PLLM2, and PLLD) have a dedicated 1.8 V analog supply. It is
important to have filtering on the supply pins that covers a broad frequency range. Each 1.15 V PLL supply pin
should have individual high frequency filtering in the form of a ferrite bead and a 0.1 µF ceramic capacitor. These
components should be located very close to the individual PLL supply balls. The impedance of the ferrite bead
should far exceed that of the capacitor at frequencies above 10 MHz. The 1.15 V to the PLL supply pins should
also have low frequency filtering in the form of an RC filter. This filter can be common to all the PLLs. The
voltage drop across the resistor is limited by the 1.15 V regulator tolerance and the DLPC900 voltage tolerance.
A resistance of 0.36 Ω and a 100 µF ceramic are recommended. Figure 37 shows the recommended filter
topology.
Figure 37. Recommended Filter Topology for PLL 1.15-V Supplies


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