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AD5399 Arkusz danych(PDF) 5 Page - Analog Devices |
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AD5399 Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 12 page AD5399 Rev. D | Page 5 of 12 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5399 TOP VIEW (Not to Scale) CLK 1 SDI 2 DGND 3 VOUTB 4 VOUTA 5 CS VTP VDD AGND VBZ 10 9 8 7 6 Figure 3. MSOP-10 Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Serial Clock Input. Positive edge triggered. 2 SDI Serial Data Input. MSB first format. 3 DGND Digital Ground. 4 VOUTB DAC B Voltage Output (A0 = Logic 1). 5 VOUTA DAC A Voltage Output (A0 = Logic 0). 6 VBZ 2 V, Virtual Bipolar Zero (Active Output). 7 AGND Analog Ground. 8 VDD Positive Power Supply. Specified for operation at 5 V. 9 VTP Connect to VDD. Reserved for factory testing. 10 CS Chip Select (Frame Sync Input). Allows clock and data to shift into the shift register when CS goes from high to low. After the 16th clock pulse, it is not necessary to bring CS high to shift the data to the output. However, CS should be brought high any time after the 16th clock positive edge in order to allow the next programming cycle. Table 5. Serial Data-Word Format ADDR DATA B15 B14 B13 B12 B11 B10 … B3 B2 B1 B0 A0 X SD 0 D11 D10 … D3 D2 D1 D0 MSB LSB A0 Address Bit. Logic low selects DAC A and logic high selects DAC B. Both channels are shut down when the SD bit is high. However, the A0 bit must be at the same state for shutdown activation and deactivation. See the Shutdown Function section. X Don’t Care. SD Shutdown Bit. Logic high puts both DAC outputs and VBZ into high impedance. A0 bit must be at the same state for shutdown activation and deactivation. 0 B12 must be 0. D0–D11 Data Bits. |
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