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MSP430F2619 Arkusz danych(PDF) 20 Page - Texas Instruments |
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MSP430F2619 Arkusz danych(HTML) 20 Page - Texas Instruments |
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20 / 120 page  20 MSP430F2619, MSP430F2618, MSP430F2617, MSP430F2616 MSP430F2419, MSP430F2418, MSP430F2417, MSP430F2416 SLAS541L – JUNE 2007 – REVISED MAY 2020 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F2619 MSP430F2618 MSP430F2617 MSP430F2616 MSP430F2419 MSP430F2418 MSP430F2417 MSP430F2416 Specifications Copyright © 2007–2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. (3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5 Specifications 5.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Voltage applied at VCC to VSS –0.3 4.1 V Voltage applied to any pin(2) –0.3 VCC + 0.3 V Diode current at any device terminal –2 2 mA Storage temperature, Tstg (3) Unprogrammed device –55 150 °C Programmed device –55 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. 5.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250 (1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up. (2) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the specified maximum frequency. (3) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. 5.3 Recommended Operating Conditions Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted) MIN MAX UNIT VCC Supply voltage (AVCC = DVCC = VCC (1)) During program execution 1.8 3.6 V During flash program or erase 2.2 3.6 VSS Supply voltage (AVSS = DVSS = VSS) 0 0 V TA Operating free-air temperature T version –40 105 °C fSYSTEM Processor frequency (maximum MCLK frequency)(2)(3) (see Figure 5-1) VCC = 1.8 V, Duty cycle = 50% ±10% DC 4.15 MHz VCC = 2.7 V, Duty cycle = 50% ±10% DC 12 VCC ≥ 3.3 V, Duty cycle = 50% ±10% DC 16 |
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