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MSP430FR6007 Arkusz danych(PDF) 29 Page - Texas Instruments

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Numer części MSP430FR6007
Szczegółowy opis  MSP430FR600x Ultrasonic Sensing MSP430??Microcontrollers for Water?멝etering Applications
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Strona internetowa  http://www.ti.com
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MSP430FR6007 Arkusz danych(HTML) 29 Page - Texas Instruments

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MSP430FR6007, MSP430FR6005
www.ti.com
SLASEV3 – MARCH 2020
Submit Documentation Feedback
Product Folder Links: MSP430FR6007 MSP430FR6005
Specifications
Copyright © 2020, Texas Instruments Incorporated
(1)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2)
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and fMCLK = fSMCLK =
fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio, fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
(3)
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
(4)
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
(5)
See for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit
using the typical data shown in Section 5.4.
(6)
Program and data reside entirely in RAM. All execution is from RAM.
(7)
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
5.4
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)
(1) (2)
PARAMETER
EXECUTION
MEMORY
VCC
FREQUENCY (fMCLK = fSMCLK)
UNIT
1 MHz
0 WAIT
STATES
(NWAITSx = 0)
4 MHz
0 WAIT
STATES
(NWAITSx = 0)
8 MHz
0 WAIT
STATES
(NWAITSx = 0)
12 MHz
1 WAIT STATE
(NWAITSx = 1)
16 MHz
1 WAIT STATE
(NWAITSx = 1)
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM, FRAM_UNI
(Unified memory)(3)
FRAM
3.0 V
225
665
1275
1550
1970
µA
IAM, FRAM (0%)
(4) (5)
FRAM
0% cache hit
ratio
3.0 V
420
1455
2850
2330
3000
µA
IAM, FRAM (50%)
(4) (5)
FRAM
50% cache hit
ratio
3.0 V
275
855
1022
1650
1888
1770
2041
2265
2606
µA
IAM, FRAM (66%)
(4) (5)
FRAM
66% cache hit
ratio
3.0 V
220
650
1240
1443
1490
1735
1880
2197
µA
IAM, FRAM (75%)
(4) (5)
FRAM
75% cache hit
ratio
3.0 V
192
261
535
1015
1170
1290
1490
1620
1870
µA
IAM, FRAM (100%)
(4) (5)
FRAM
100% cache hit
ratio
3.0 V
125
237
450
670
790
µA
IAM, RAM
(6) (5)
RAM
3.0 V
140
323
590
880
1070
µA
IAM, RAM only
(7) (5)
RAM
3.0 V
90
182
292
540
830
1020
1313
µA


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