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ADD8502 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADD8502 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 16 page REV. 0 ADD8502 –6– Pin No. Mnemonic Name I/O Description 21 REV2 Reference Output I When PSK is HIGH and GS1 or GS2 is LOW, then INVERT selects the output Select levels on V0 to V4. If INVERT is HIGH, outputs V0 to V4 are connected to reference levels VP0 to VP4, respectively. If INVERT is LOW, outputs V0 to V4 are connected to reference levels VN0 to VN4, respectively. When PSK is HIGH and GS1 and GS2 are HIGH, V1–V3 are, Hi-Z state, but V0 and V4 are still connected to reference levels VP0 and VP4 when INVERT is HIGH. Outputs V0 and V4 switch to VN0 and VN4 when REV is LOW. 22 GS2 Sleep Mode I When GS1 and GS2 are HIGH, the middle three output buffers are shut down Select and V1, V2, and V3 are put into Hi-Z states. Other combinations of GS1 and GS2 leave the outputs of A1 to A3 fully active. 23 GS1 Sleep Mode I When GS1 and GS2 are HIGH, the middle three output buffers are shut down Select and V1, V2, and V3 are Hi-Z. Other combinations of GS1 and GS2 leave the outputs of A1 to A3 fully active. 24 PSK Global Power I When PSK is pulled LOW, the chip will be put into the full Power-Down Mode. Shutdown The DACs, resistor ladder network preamps, and output buffers will all be shut down, and A0 to A4 will be in Hi-Z states. Recovery from full power-down to normal operation is within 30 µs. All digital inputs accept CMOS or TTL logic levels. |
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