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ST7LITE3 Arkusz danych(PDF) 67 Page - STMicroelectronics |
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ST7LITE3 Arkusz danych(HTML) 67 Page - STMicroelectronics |
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67 / 167 page  ST7LITE3 67/167 DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d) Bit 4 = BPEN Break Pin Enable. This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled Bit 3:0 = PWM[3:0] Break Pattern. These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active. PWMx DUTY CYCLE REGISTER HIGH (DCRxH) Read / Write Reset Value: 0000 0000 (00h) PWMx DUTY CYCLE REGISTER LOW (DCRxL) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved. Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value This 12-bit value is written by software. It defines the duty cycle of the corresponding PWM output signal (see Figure 36). In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see Figure 36). In Output Compare mode, they define the value to be com- pared with the 12-bit upcounter value. INPUT CAPTURE REGISTER HIGH (ATICRH) Read only Reset Value: 0000 0000 (00h) INPUT CAPTURE REGISTER LOW (ATICRL) Read only Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved. Bits 11:0 = ICR[11:0] Input Capture Data. This is a 12-bit register which is readable by soft- ware and cleared by hardware after a reset. The ATICR register contains captured the value of the 12-bit CNTR1 register when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS). Capture will only be performed when the ICF flag is cleared. TIMER CONTROL REGISTER2 (ATCSR2) Read/Write Reset Value: 0000 0011 (03h) Bits 7:6 = Reserved. Forced by hardware to 0. Bit 5 = ICS Input Capture Shorted This bit is read/write by software. It allows the AT- timer CNTR1 to use the LTIC pin for long input capture. 0 : ATIC for CNTR1 input capture 1 : LTIC for CNTR1 input capture 15 8 0 0 0 0 DCR11 DCR10 DCR9 DCR8 7 0 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 15 8 0 0 0 0 ICR11 ICR10 ICR9 ICR8 7 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 7 0 0 0 ICS OVFIE2 OVF2 ENCNT R2 TRAN2 TRAN1 1 |
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