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AD5290YRMZ100 Arkusz danych(PDF) 9 Page - Analog Devices |
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AD5290YRMZ100 Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 11 page Preliminary Technical Data AD5290 Rev. Pr C | Page 9 of 11 A VI W B VO Figure 7. Potentiometer Mode Configuration Ignoring the effect of the wiper resistance, the transfer function is simply A W V 256 D ) D ( V = (3) A more accurate calculation, which includes the wiper resistance effect, yields A W W AB W V R 2 R R 256 D ) D ( V + + = AB R (4) If there is an applied voltage at the B terminal, then the transfer function becomes B A W V D V D D V 256 256 256 ) ( − + = (5) Unlike in rheostat mode operation where the absolute tolerance is high, potentiometer mode operation yields an almost ratio- metric function of D/256 with a relatively small error contributed by the RW terms, and therefore the tolerance effect is almost cancelled. Although the thin film step resistor RS and CMOS switches resistance RW have very different temperature coeffi- cients, the ratiometric adjustment also reduces the overall temperature coefficient effect to 5 ppm/°C, except at low value codes where RW dominates. Potentiometer mode operations include others such as op amp input, feedback resistor networks, and other voltage scaling applications. A, W, and B terminals can in fact be input or output terminals provided that |VA|, |VW|, and |VB| do not exceed |VDD| and |VSS|. SPI COMPATIBLE 3-WIRE SERIAL BUS The AD5290 contains a 3-wire SPI compatible digital interface (SDI, CS, and CLK). The 8-bit serial word must be loaded MSB first. The format of the word is shown in Table . The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. CS should start high, when it goes low, the clock loads data into the serial register on each positive clock edge (see Figure 3). The data setup and data hold times in the specification table determine the valid timing requirements. The AD5290 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the CS returns to logic high. If dataword contains more than 8-bit, the extra MSB bits will be ignored. ESD PROTECTION All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in 8 and Figure 9. This applies to the digital input pins SDI, CLK, and CS. LOGIC 340 Ω VSS Figure 8. ESD Protection of Digital Pins A,B,W VSS Figure 9. ESD Protection of Resistor Terminals TERMINAL VOLTAGE OPERATING RANGE The AD5290 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or GND will be clamped by the internal forward biased diodes (see Figure 10). A VDD B W VSS Figure 10. Maximum Terminal Voltages Set by VDD and VSS POWER-UP SEQUENCE Since the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 10), it is important to power VDD–to-GND and VSS-to-GND before applying any voltage to terminals A, B, and W; otherwise, the diode will be forward biased such that VDD will be powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VSS,VDD, digital inputs, and then |
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