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74ABTH16821ADL Arkusz danych(PDF) 6 Page - NXP Semiconductors |
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74ABTH16821ADL Arkusz danych(HTML) 6 Page - NXP Semiconductors |
6 / 10 page Philips Semiconductors Product specification 74ABT16821A 74ABTH16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 1998 Feb 27 6 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT MIN TYP MAX MIN MAX fMAX Maximum clock frequency 1 160 250 160 MHz tPLH tPHL Propagation delay nCP to nQx 1 1.3 1.1 2.4 2.0 3.3 2.6 1.3 1.1 3.7 3.0 ns tPZH tPZL Output enable time to High and Low level 3 4 1.4 1.2 2.5 2.3 3.3 3.0 1.4 1.2 4.1 3.7 ns tPHZ tPLZ Output disable time from High and Low level 3 4 1.6 1.3 3.2 2.3 4.1 3.1 1.6 1.3 4.8 3.3 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT MIN TYP MIN MAX ts(H) ts(L) Setup time, High or Low nDx to nCP 2 1.8 1.8 1.2 –0.9 1.8 1.8 ns th(H) th(L) Hold time, High or Low nDx to nCP 2 1.0 1.0 0.8 –1.0 1.0 1.0 ns tw(H) tw(L) nCP pulse width High or Low 1 2.5 2.5 0.8 1.0 2.5 2.5 ns AC WAVEFORMS VM SH00005 nCP nQx VM tw(H) tPHL VM tPLH 1/fMAX VM VM tw(L) 0V VOH VOL 3.0V or VCC whichever is less Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock frequency th(H) ts(H) CP SH00006 VM VM VM VM VM VM th(L) ts(L) nDx 0V 0V 3.0V or VCC whichever is less 3.0V or VCC whichever is less Waveform 2. Data Setup and Hold Times VY VM VM VM nQx tPZH tPHZ SH00007 nOE 0V VOH 0V 3.0V or VCC whichever is less Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level VX VM VM VM nQx tPZL tPLZ SH00008 nOE VOL 0V 0V 3.0V or VCC 3.0V or VCC whichever is less Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level |
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