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GS74108ATP-8 Arkusz danych(PDF) 5 Page - GSI Technology |
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GS74108ATP-8 Arkusz danych(HTML) 5 Page - GSI Technology |
5 / 13 page DQ VT = 1.4 V 50 Ω 30pF1 DQ 3.3 V Output Load 1 Output Load 2 589 Ω 434 Ω 5pF1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ Parameter Conditions Input high level VIH = 2.4 V Input low level VIL = 0.4 V Input rise time tr = 1 V/ns Input fall time tf = 1 V/ns Input reference level 1.4 V Output reference level 1.4 V Output load Fig. 1& 2 GS74108ATP/J/X Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.07 1/2006 5/13 © 2001, Giga Semiconductor, Inc. AC Test Conditions AC Characteristics Read Cycle Parameter Symbol -8 -10 -12 Unit Min Max Min Max Min Max Read cycle time t 8 — 10 — 12 — ns Address access time t — 8 — 10 — 12 ns Chip enable access time (CE) t — 8 — 10 — 12 ns Output enable to output valid (OE) t — 3.5 — 4 — 5 ns Output hold from address change t 3 — 3 — 3 — ns Chip enable to output in low Z (CE) t * 3 — 3 — 3 — ns Output enable to output in low Z (OE) t * 0 — 0 — 0 — ns Chip disable to output in High Z (CE) t * — 4 — 5 — 6 ns Output disable to output in High Z (OE) t * — 3.5 — 4 — 5 ns * These parameters are sampled and are not 100% tested. RC AA AC OE OH LZ OLZ HZ OHZ |
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