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74ABT834 Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74ABT834 Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 7 page Philips Semiconductors Advanced BiCMOS Products Objective specification 74ABT834 Octal inverting transceiver with parity generator/checker (3–State) June 9, 1992 2 PIN DESCRIPTION SYMBOL PIN NUMBER NAME AND FUNCTION A0 – A7 2, 3, 4, 5, 6, 7, 8, 9 A port 3–State inputs/outputs B0 – B7 23, 22, 21, 20, 19, 18, 17, 16 B port 3–State inputs/outputs OEA 1 Enables the A outputs when Low OEB 14 Enables the B outputs when Low PARITY 15 Parity output ERROR 10 Error output CLEAR 11 Clears the error flag register when Low CP 13 Clock input GND 12 Ground (0V) VCC 24 Positive supply voltage FUNCTION TABLE INPUTS OUTPUTS MODE OEB OEA An Σ of Highs Bn + Parity Σ of Lows An Bn PARITY A data to B bus and generate odd parity output L H Odd Even NA (output) NA (input) An H L B data to A bus and check for parity error1 H L NA (output) Odd Even Bn NA (input) NA (input) A bus and B bus disabled2 H H X X Z Z Z A data to B bus and generate inverted parity output L L Odd Even NA (output) NA (input) An L H NOTES: 1. Error checking is detailed in the Error Flag Function Table below. 2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd. ERROR FLAG FUNCTION TABLE INPUTS Internal node Output MODE CLEAR CP Bn + Parity Σ of Lows Point ”P” Pre–state ERRORn–1 ERROR OUTPUT Sample H H H ↑ ↑ X Odd Even X H L X H X L H L L Hold H ↑ X X X NC Clear L X X X X H H = High voltage level steady state L = Low voltage level steady state X = Don’t care NA = Not applicable NC = No change Z = High impedance ”off” state ↑ = Low–to–High clock transition ↑ = Not a Low–to–High clock transition |
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