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74ALVCH16373DGG Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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2 / 12 page Philips Semiconductors Product specification 74ALVCH16373 16-bit D-type transparent latch (3-State) 2 1999 Sep 20 853-2086 22418 FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple V CC and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • All data inputs have bus hold • Output drive capability 50Ω transmission lines @ 85°C • Current drive ±24 mA at 3.0 V DESCRIPTION The 74ALVCH16373 is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. One latch enable (LE) input and one output enable (OE) are provided per 8-bit section. The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q5 GND 1Q6 1Q7 2Q0 2Q1 GND 1Q4 2Q2 2Q3 VCC 2Q4 2Q5 2D5 2D4 VCC 2D3 2D2 GND 2D1 2D0 1D7 1D6 GND 1D5 1D4 VCC 1D3 1D2 GND 1D1 1D0 1LE 21 22 23 24 25 26 27 28 GND 2Q6 2Q7 2OE 2LE 2D7 2D6 GND SW00066 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay VCC = 2.5V, CL = 30pF 2.1 t /t gy Dn to Qn VCC = 3.3V, CL = 50pF 2.1 ns tPHL/tPLH Propagation delay VCC = 2.5V, CL = 30pF 2.2 ns gy LE to Qn VCC = 3.3V, CL = 50pF 2.2 CI Input capacitance 5.0 pF C Power dissipation capacitance per latch V = GND to VCC1 Outputs enabled 16 pF CPD Power dissipation capacitance per latch VI = GND to VCC1 Outputs disabled 10 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III –40 °C to +85°C 74ALVCH16373 DL ACH16373 DL SOT370-1 48-Pin Plastic TSSOP Type II –40 °C to +85°C 74ALVCH16373 DGG ACH16373 DGG SOT362-1 |
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