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STK12C68-C45IM Arkusz danych(PDF) 8 Page - List of Unclassifed Manufacturers

Numer części STK12C68-C45IM
Szczegółowy opis  CMOS nvSRAM 8K x 8 AutoStore Nonvolatile Static RAM Industrial Temperature/Military Screen
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STK12C68-C45IM Arkusz danych(HTML) 8 Page - List of Unclassifed Manufacturers

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48
STK12C68-IM
may optionally be pulled to VCCX via an external
resistor with a value such that the combined load of the
resistor and all parallel chip connections does not
exceed IHSB_OL at VOL. Do not connect this or any
other pull-up to the VCAP node.
If HSB is to be connected to external circuits other than
other STK12C68-IMs, an external pull-up resistor
should be used.
During any STORE operation, regardless of how it was
initiated, the STK12C68-IM will continue to drive the
HSB pin low, releasing it only when the STORE is
complete. Upon completion of a STORE operation, the
part will be disabled until HSB actually goes HIGH.
AUTOMATIC
STORE OPERATION
During normal operation, the STK12C68-IM will draw
current from VCCX to charge up a capacitor connected
to the VCAP pin. This stored charge will be used by the
chip to perform a single STORE operation. After power
up, when the voltage on the VCAP pin drops below
VSWITCH, the part will automatically disconnect the
VCAP pin from VCCX and initiate a STORE operation.
Figure 1 shows the proper connection of capacitors for
automatic store operation. The charge storage capaci-
tor should have a capacity of at least 100
µF (± 20%) at
6V. Each STK12C68-IM must have its own 100
µF
capacitor.
Each STK12C68-IM
must have a high
quality, high frequency bypass capacitor of 0.1
µF
connected between VCAP and VSS, using leads and
traces that are as short as possible.
If the
AutoStore™ function is not required, then VCAP
should be tied directly to the power supply and VCCX
should be tied to ground. In this mode, STORE opera-
tions may be triggered through software control or the
HSB pin. In either event, VCAP (Pin 1) must always
have a proper bypass capacitor connected to it.
In order to prevent unneeded STORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
WRITE
operation has taken place since the most recent
STORE
cycle. Note that if HSB is driven low via external
circuitry and no WRITEs have taken place, the part will
still be disabled until HSB is allowed to return HIGH.
Software initiated STORE cycles are performed regard-
less of whether or not a WRITE operation has taken
place.
EEPROM
cells. The nonvolatile data can be recalled an
unlimited number of times.
AUTOMATIC RECALL
During power-up, or after any low power condition
(VCAP < VSWITCH), when VCAP exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated.
If the STK12C68-IM is in a WRITE state at the end of
power-up RECALL , the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor should
be connected between W and system VCC.
HARDWARE PROTECT
The STK12C68-IM offers hardware protection against
inadvertent
STORE operation
during low voltage
conditions.
When VCAP < VSWITCH, all externally
initiated STORE operations will be inhibited.
HSB OPERATION
The Hardware Store Busy pin (HSB) is an open drain
circuit acting as both input and output to perform two
different functions. When driven low by the internal
chip circuitry it indicates that a STORE operation (initi-
ated via any means) is in progress within the chip.
When driven low by external circuitry for longer than
tASSERT, the chip will conditionally initiate a STORE
operation after tDELAY.
READ
and WRITE operations that are in progress when
HSB is driven low (either by internal or external cir-
cuitry) will be allowed to complete before the STORE
operation is performed, in the following manner. After
HSB goes low, the part will continue normal SRAM
operations for tDELAY. During tDELAY, a transition on
any address or control signal will terminate SRAM
operation and cause the STORE to commence. Note
that if an SRAM write is attempted after HSB has been
forced low, the write will not occur and the
STORE
operation will begin immediately.
HARDWARE-STORE-BUSY (HSB) is a high speed,
low drive capability bi-directional control line. In order
to allow a bank of STK12C68-IMs to perform synchro-
nized STORE functions, the HSB pin from a number of
chips may be connected together. Each chip contains
a small internal current source to pull HSB HIGH when
it is not being driven low. To decrease the sensitivity
of this signal to noise generated on the PC board, it


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