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54298 Arkusz danych(PDF) 3 Page - National Semiconductor (TI) |
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54298 Arkusz danych(HTML) 3 Page - National Semiconductor (TI) |
3 / 4 page Switching Characteristics VCC ea50V TA ea25 C (See Section 1 for test waveforms and output load) CL e 15 pF Symbol Parameter RL e 400X Units Min Max tPLH Propagation Delay CP to Qn 27 ns tPHL 32 Functional Description This device is a high speed quad 2-port register It selects four bits of data from two sources (ports) under the control of a Common Select input (S) The selected data is trans- ferred to the 4-bit output register synchronous with the HIGH-to-LOW transition of the Clock input (CP) The 4-bit output register is fully edge-triggered The Data inputs (Inx) and Select input (S) need be stable only one setup time prior to the HIGH-to-LOW transition of the clock for predict- able operation Truth Table Inputs Output SI0x I1x Qx II X L Ih X H hX l L hX h H l e LOW Voltage Level one setup time prior to the HIGH-to-LOWclock transition h e HIGH Voltage Level one setup time prior to the HIGH-to-LOW clock transition H e HIGH Voltage level L e LOW Voltage level X e Immaterial Logic Diagram TLF10215 – 3 3 |
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