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74LV02N Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74LV02N Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74LV02 Quad 2-input NOR gate 2 1998 Apr 20 853–1899 19257 FEATURES • Wide operating voltage: 1.0 to 5.5 V • Optimized for low voltage applications: 1.0 to 5.5 V • Accepts TTL input levels between V CC = 2.7 V and VCC = 3.6 V • Typical V OLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C • Typical V OHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Output capability: standard • I CC category: SSI DESCRIPTION The 74LV02 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT02. The 74LV02 provides the 2-input NOR function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nA, nB to nY CL = 15 pF; VCC = 3.3 V 6 ns CI Input capacitance 3.5 pF CPD Power dissipation capacitance per gate See Notes 1 and 2 22 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL –40 °C to +125°C 74LV02 N 74LV02 N SOT27-1 14-Pin Plastic SO –40 °C to +125°C 74LV02 D 74LV02 D SOT108-1 14-Pin Plastic SSOP Type II –40 °C to +125°C 74LV02 DB 74LV02 DB SOT337-1 14-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV02 PW 74LV02PW DH SOT402-1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1, 4, 10, 13 1Y – 4Y Data outputs 2, 5, 8, 11 1A – 4A Data inputs 3, 6, 9, 12 1B – 4B Data inputs 7 GND Ground (0 V) 14 VCC Positive supply voltage FUNCTION TABLE INPUTS OUTPUTS nA nB nY L L H L H L H L L H H L NOTES: H = HIGH voltage level L = LOW voltage level |
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