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74LV107N Arkusz danych(PDF) 7 Page - NXP Semiconductors

Numer części 74LV107N
Szczegółowy opis  Dual JK flip-flop with reset; negative-edge trigger
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV107N Arkusz danych(HTML) 7 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
1998 Apr 20
7
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6 V;
VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
SV00504
1/f max
t h
t h
t PLH
t PHL
t PLH
t PHL
t W
t su
t su
VM
VM
VM
VM
nJ, nK
INPUT
nCP
INPUT
nQ
OUTPUT
VI
VI
GND
GND
VOH
VOH
VOL
VOL
nQ
OUTPUT
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the J and K to nCP set-up and hold times
and the maximum clock pulse frequency.
SV00502
tW
t PHL
t PLH
t rem
VM
VM
VM
nR
INPUT
nCP
INPUT
nQ
OUTPUT
VOH
VI
VI
VOH
VOL
VOL
GND
GND
nQ
OUTPUT
Figure 2. Reset (nR) input to output (nQ, nQ) propagation
delays, the reset pulse width and the nR to nCP removal time.
TEST CIRCUIT
PULSE
GENERATOR
RT
Vl
D.U.T.
VO
CL
RL= 1k
Vcc
Test Circuit for Outputs
DEFINITIONS
VCC
VI
< 2.7V
2.7–3.6V
VCC
2.7V
TEST
tPLH/tPHL
≥ 4.5 V
VCC
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
50pF
RT = Termination resistance should be equal to ZOUT of pulse generators.
SV00902
Figure 3. Load circuitry for switching times.


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