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74LV107D Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74LV107D Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74LV107 Dual JK flip-flop with reset; negative-edge trigger 2 1998 Apr 20 853–1904 19255 FEATURES • Wide operating: 1.0 to 5.5 V • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between V CC = 2.7 V and VCC = 3.6 V • Typical V OLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C • Typical V OHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Output capability: standard • I CC category: flip-flops DESCRIPTION The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nCP to nQ nCP to nQ nR to nQ, nQ CL = 15 pF; VCC = 3.3 V 15 15 15 ns fmax Maximum clock frequency 77 MHz CI Input capacitance 3.5 pF CPD Power dissipation capacitance per flip-flop VI = GND to VCC1 30 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL –40 °C to +125°C 74LV107 N 74LV107 N SOT27-1 14-Pin Plastic SO –40 °C to +125°C 74LV107 D 74LV107 D SOT108-1 14-Pin Plastic SSOP Type II –40 °C to +125°C 74LV107 DB 74LV107 DB SOT337-1 14-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV107 PW 74LV107PW DH SOT402-1 PIN CONFIGURATION SV00497 1J 1Q 1Q 1K 2Q 2Q GND 1R 1CP 2K 2R 2CP 2J 14 13 12 11 10 9 8 1 2 3 4 5 6 7 VCC PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1, 8, 4, 11 1J, 2J, 1K, 2K Synchronous inputs; flip-flops 1 and 2 2, 6 1Q, 2Q Complement flip-flop outputs 3, 5 1Q, 2Q True flip-flop outputs 7 GND Ground (0 V) 12, 9 1CP, 2CP Clock input (HIGH-to-LOW, edge-triggered) 13, 10 1R, 2R Asynchronous reset inputs (active LOW) 14 VCC Positive supply voltage |
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