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74LV109DB Arkusz danych(PDF) 7 Page - NXP Semiconductors

Numer części 74LV109DB
Szczegółowy opis  Dual JK flip-flop with set and reset; positive-edge trigger
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV109DB Arkusz danych(HTML) 7 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 20
7
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SV00522
1/f max
t h
t h
t PLH
t PHL
t PLH
t PHL
t W
t su
t su
VM
VM
VM
VM
nJ, nK
INPUT
nCP
INPUT
nQ
OUTPUT
VI
VI
GND
GND
VOH
VOH
VOL
VOL
nQ
OUTPUT
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the nJ and nK to nCP set-up, the nCP to
nJ, nK hold times and the maximum clock pulse frequency.
SV00523
tW
tW
tPLH
tPHL
trem
VM
VM
VM
VM
VM
nSD
INPUT
nRD
INPUT
nCP
INPUT
nQ
OUTPUT
VOH
Vl
Vl
Vl
VOH
VOL
VOL
GND
GND
GND
nQ
OUTPUT
trem
tPLH
tPHL
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths and the nRD,
nSD to nCP removal time.
TEST CIRCUIT
PULSE
GENERATOR
RT
VI
D.U.T.
VO
CL
RL = 1k
VCC
Test Circuit for switching times
DEFINITIONS
VCC
VI
< 2.7V
VCC
TEST
tPLH/tPHL
RT = Termination resistance should be equal to ZOUT of pulse generators.
50pF
SV00901
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
2.7–3.6V
2.7V
Figure 3. Load circuitry for switching times.


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